The introduction of programmable logic devices (PLDs) was a true revolution in the hardware design world. It enabled engineers to shrink circuits requiring several devices onto a single device thus simplifying their designs while saving space and power. Traditionally, PLDs have been used in combinational circuits such as address decoders as well as sequential circuits such as bus arbitration schemes. During the last few years, advances and improvements in PLD architectures enabled the devices to grow more complex while addressing the never-ending quest for higher density and faster speeds. Despite these improvements, engineers still face certain problems and limitations when implementing state machine designs with PLDs.
A typical programmable logic device is composed of a user-programmable AND array, a fixed or programmable OR gate or array, followed by a macrocell comprising output registers, a feedback path to the programmable AND array, and output pads. The existence of a feedback path from the output registers or buffers to the AND array makes PLDs ideal candidates for state machine implementations.
Although the feedback paths allow for architecture that implements state machines these architectures have been encumbered with inefficient feedback paths. Specifically, these paths have incorporated unnecessary gate delays like three-states or registers.
For example, FIG. 1, is a related design which implements an inefficient feedback path. Particularly, while in an output mode, programmable logical OR array 10 couples signals to three-state (output buffer) 12 where signals are coupled to output pad 14 and input buffer 16 via feedback line 18.
One skilled in the art will understand that a three-state, such as 12, has a relatively large signal delay and creates a large amount of signal noise. Additionally, it is easily noted that there is no exclusive feedback line, but a sharing of the feedback and input line.
Therefore, a need exists for a macrocell which has an efficient feedback path, yet provides for an input line from the I/O pad. Particularly, a feedback path which avoids costly timing delays and unnecessary signal noise being injected (returned) into the logic array.